The present invention relates to a semiconductor design technology, and more particularly, to a semiconductor memory device for generating a column selection signal activated in response to a read operation and a write operation.
Generally, a semiconductor memory device such as a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) stores or outputs data according to a command required by, i.e., a Central Processing Unit (CPU). If the CPU requires a write operation, data are stored into a memory cell that corresponds to an address inputted from the CPU; if the CPU requires a read operation, data stored in a memory cell that corresponds to an address inputted from the CPU are outputted.
FIG. 1 is a diagram for explaining a general read operation and write operation of a semiconductor memory device. For reference, the semiconductor memory device is designed to include more than tens of millions of memory cells these days. In order to explain conveniently, a single memory cell is illustrated and is referred to as a reference numeral of 110.
The read operation of the semiconductor memory device will be briefly described referring to FIG. 1.
Firstly, if a word line (WL), which is selected by decoding a row address inputted according to an external command signal, is activated, a cell transistor T1 of the memory cell 110 is turned-on and data stored in a cell capacitor C1 are charge-shared to one line of pre-charged bit line pair BL and /BL (a bit line BL in FIG. 1). A bit line BL and a bit line bar /BL have a fine voltage difference through the charge-sharing operation. For the reference, a pre-charged voltage level is half of a voltage level of a core voltage, which is an internal voltage.
Thereafter, a bit line sense amplifying unit 120 senses a fine voltage difference between the bit line BL and the bit line bar /BL which corresponds to the bit line BL and amplifies it. In other words, in case that an electric potential of the bit line BL is higher than that of the bit line bar /BL, the bit line BL is amplified to a pull-up power supply voltage RTO and the bit line bar /BL is amplified to a pull-down power supply voltage SB. On the contrary, in case that the electric potential of the bit line BL is lower than that of the bit line bar /BL, the bit line BL is amplified to the pull-down power supply voltage SB and the bit line bar /BL is amplified to the pull-up power supply voltage RTO.
Meanwhile, if a column selection signal YI, which is selected by decoding a column address inputted according to the external command signal, is activated, a column selection unit 130 is enabled so that the bit line pair BL and /BL are connected to segment input/output line pair SIO and /SIO. That is, the amplified data on the bit line BL are transferred to the segment input/output line SIO and the amplified data on the bit line bar /BL are transferred to the segment input/output line bar /SIO. Herein, the column selection signal YI is a signal that has a predetermined pulse width and will be explained again hereafter.
Thereafter, if an input/output switching unit 140 is enabled in response to an input/output control signal CTR_IO, the segment input/output line pair SIO and /SIO are connected to local input/output line pair LIO and /LIO. That is, the data transferred to the segment input/output line SIO are transferred to the local input/output line LIO and the data transferred to the segment input/output line bar /SIO are transferred to the local input/output line bar /LIO. A read driving unit 150 drives a global input/output line GIO according to the data transferred through the local input/output line pair LIO and /LIO.
As a result, the data stored in the memory cell 110 are amplified at the bit line pare BL and /BL and is transferred to the segment input/output line pair SIO and /SIO. The data transferred to the segment input/output line pair SIO and /SIO are transferred to the local input/output line pair LIO and /LIO in response to the column selection signal YI. And, the data transferred to the local input/output line pair LIO and /LIO are transferred to the global input/output line GIO in response to the input/output control signal CTR_IO. The data transferred in this manner are finally outputted to the outside through a corresponding pad (not shown in the drawing).
Meanwhile, in the write operation, data inputted from the outside are transferred in a reverse direction in comparison with the read operation. That is, the data inputted through a pad are transferred from the global input/output line GIO to the local input/output line pair LIO and /LIO through a write driving unit 160, and from the local input/output line pair LIO and /LIO to the segment input/output line pair SIO and /SIO, and from the segment input/output line pair SIO and /SIO to the bit line bar pair BL and /BL. The data transferred in this manner are finally stored into the memory cell 110.
For reference, an RC loading is reflected to the data transferred through each line by a plurality of resistors R and capacitors C.
FIG. 2 is a block diagram for explaining a construct that participates in the generation of the column selection signal YI. A pulse width determination unit 210, a delay unit 230 and an address decoding unit 250 are shown in the drawing.
The pulse width determination unit 210 generates a pulse determining signal AYP18 and a set control signal SET in response to a read command signal CASP10RD, a write command signal CASP10WT and a reset control signal SETB. Herein, the read command signal CASP10RD is activated in the read operation of the semiconductor memory device, which is defined by an external command signal. The write command signal CASP10WT is activated in the write operation of the semiconductor memory device, which is defined by an external command signal. And, the pulse determining signal AYP18 is activated in response to the read command signal CASP10RD and the write command signal CASP10WT and is deactivated in response to the reset control signal SETB. Continuously, the set control signal SET is activated in response to the read command signal CASP10RD and the write command signal CASP10WT.
The delay unit 230 generates the reset control signal SETB by delaying the set control signal SET for a predetermined time. Herein, the delay unit 230 may designed to include a plurality of capacitors and resistors.
The address decoding unit 250 receives the pulse determining signal AYP18 and a plurality of column address signals ADD<0:N> where the N is a natural number to generate the column selection signal YI. Herein, the column selection signal YI is selected by the column address signal ADD<0:N> and has the same pulse width as the pulse determining signal AYP18. Although only a single column selection signal YI is shown in the drawing for explaining conveniently, actually the column selection signal YI is one of a plurality of signals generated by decoding the column address signal ADD<0:N>.
In other words, the column address signal ADD<0:N> is reflected to the pulse determining signal AYP18 generated by the pulse width determination unit 210 so that the column selection signal YI is generated. Herein, the pulse width of the pulse determining signal AYP18 is described in detail.
The pulse width of the pulse determining signal AYP18 corresponds to the delay time taken in the delay unit 230. That is, the pulse determining signal AYP18 is activated in response to the set control signal SET activated in response to the read command signal CASP10RD and the write command signal CASP10WT and is deactivated in response to the reset control signal SETB which is generated by delaying the set control signal SET for the predetermined time in the delay unit 230. As a result, pulse determining signal AYP18 has the pulse width that corresponds to the delay time taken in the delay unit 230.
Herein, the delay unit 230 is designed to have an appropriate delay time that a designer determines. Therefore, in case of the semiconductor memory device whose delay time is fixed by the designer, the compatibility with an operational frequency of the system is decreased. For reference, the operational frequency is determined according to the system clock, i.e., an external clock CLK of the semiconductor memory device. That is, the semiconductor memory device designed considering a high operational frequency should be used only in a system that has a corresponding operational frequency; likewise, the semiconductor memory device designed considering a low operational frequency should be used only in a system that has a corresponding operational frequency. Of course, it is possible to use the semiconductor memory device designed considering a high operational frequency in the system that has a low operational frequency. However, since the pulse width is shortened unnecessarily, there is the problem of degrading the operational characteristics of the semiconductor memory device.
Furthermore, the delay unit 230 is sensitive to process, voltage and temperature because of characteristics of a circuit for delaying an inputted signal for a predetermined time and outputting the delayed signal. Therefore, even if the delay unit 230 is designed to have the predetermined delay time, the delay time is changed according to the process, voltage and temperature. That is, the pulse width of the pulse determining signal AYP18 is changed, which means that the stability of an operation of the circuit cannot be secured.